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Preliminary Technical Data
POWER SUPPLY MONITOR INTERRUPT (PSM)
The power supply monitor interrupt (PSM) alerts the 8052 core
of power supply events. The PSM interrupt is disabled by
default. Setting the EPSM bit in the Interrupt Enable and
Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt.
EPSR
FPSR
ESAG
FSAG
ADE7566/ADE7569
The Power Management Interrupt Enable SFR (IPSME, 0xEC)
controls the events that result in a PSM interrupt. Figure 23 is a
diagram illustrating how the PSM interrupt vector is shared
among the PSM interrupt sources. The PSM interrupt flags are
latched and must be cleared by writing to the flag register.
EVSW
FVSW
FPSM
EPSM
TRUE?
PENDING PSM
INTERRUPT
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
EPSR
FPSR
RESERVED
RESERVED
FPSM
PTI
ESAG
FSAG
RESERVED
RESERVED
RESERVED
PSI
EVSW
FVSW
EADE
EBAT
FBAT
ETI
EBSO
FBSO
EPSM
EVDCIN
FVDCIN
ESI
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
Figure 23. PSM Interrupt Sources
Rev. PrA | Page 27 of 136
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